1. Field of the Invention
The present invention relates to vacuum fluorescent display (VFD) systems having a plurality of anodes arranged in a matrix that may be selectively activated to display information. More particularly, the present invention relates to a method of driving a fluorescent display utilizing a quad-anode connection structure between the data drivers and the anodes to produce a high density and high clarity dot matrix display.
2. Discussion of Related Art
Vacuum fluorescent displays typically include a matrix of anodes that comprise the pixels of the display and at least one filament cathode that is positioned adjacent to the matrix of anodes and parallel to the plane defined by the matrix. When the system is activated, a power source heats the filament cathode, thus causing the filament to emit thermions that, in turn, are attracted toward activated anodes. Because the anodes are coated with a reactive material, the thermions that contact the activated anodes will cause those anodes to fluoresce. Therefore, by selectively activating the anodes, and thus causing those anodes to attract thermions, i.e., fluoresce, desired information may be displayed.
Typically, the anodes are selectively activated by a combination of signals from at least one anode driver and a grid driver. The anode and grid drivers, in turn, are controlled by a system processor that, among its many functions, transmits processed serial display data to the anode drivers and grid data to the grid driver. In the known display system 10 shown in FIG. 1, a matrix 12 of anodes 11 is arranged in a plurality of columns C1-C16. System 10 also has a series of adjacent grids 14 that are positioned between, and perpendicular to, the filament cathode (not shown) and matrix 12. Each grid 14 is associated with typically two equally spaced columns of closely spaced anodes 11 that extend from the top to the bottom of the display screen. When activated, grids 14 enable the anodes 11 associated therewith to fluoresce. If particular anodes 11 associated with activated grids 14 receive a logic "high" display data signal, the activated grids will attract and direct thermions emitted by the cathode toward those associated anodes 11 to insure that those anodes will fluoresce.
A system processor 20 transmits a control signal (described below) to a grid driver 40 that, in response, scans the columns of closely spaced anodes 11, typically from left to right, by sequentially activating pairs of grids 14 to enable the columns of anodes associated therewith. If particular "enabled" anodes in the currently activated grids 14 receive a logic "high" display data signal from their corresponding anode drivers 16, 18, those particular anodes will be activated and fluoresce while anodes receiving a logic "low" data signal will not be activated, and thus will not fluoresce. As grid driver 40 successively activates pairs of grids 14, active anodes (anodes associated with activated grids 14 that receive a logic "high" data signal from its corresponding anode driver) will fluoresce to display the desired display data. In other words, particular anodes will be illuminated by the combination of a scanning grid signal from grid driver 40 that activates grids 14 and enables corresponding anodes 11, and logic "high" display data signals from anode drivers 16, 18.
As shown in FIG. 1, display system 10 includes two anode drivers 16, 18 for sending data to anodes 11 of display matrix 12 via a plurality of output lines 36, 37. Two anode drivers are typically required for (an average relatively high) resolution dot matrix display due to the limited number of pins in a standard anode driver chip. A simplified 8.times.16 display is shown in FIG. 1 for ease of illustration. Displays of this type are typically much larger (e.g., 32.times.80) and the anodes are more closely spaced. In FIG. 1, one anode driver 16 transmits display data D1 signals to anodes 11 in the rows in the top half of the display matrix 12 via output lines 36 (left anode driver), and the other anode driver 18 transmits display data D2 to anodes 11 in the rows in the bottom half of display matrix 12 via output lines 37 (right anode driver). To accommodate both anode drivers, processor 20 of this system supplies serial display data D1, D2 via two output ports 22, 24.
In general, to display desired information, the display data D1, D2 is transmitted as a series of serial data bits to processor 20. Processor 20 thereafter sends the data to anode drivers 16, 18 via anode driver input ports 29, for display. (The following description is applicable to both anode drivers 16, 18 of system 10, but will be presented with respect to left anode driver 16 for illustrative purposes.) With reference to FIG. 3, anode driver 16 has a shift register 44 that receives the serial display data and stores the data one bit at a time in response to a clock signal CLK1 supplied to input port 28 from processor 20. The data is stored such that it subsequently may be output in parallel from shift register 44 to anodes 11. Then, as described in more detail below with respect to FIG. 2, processor 20 applies a strobe signal STBA to port 26 of anode driver 16, and specifically to a plurality of latch gates 45 therein corresponding to each data bit, to latch the shift register data to output lines 47 of latch gates 45, thus allowing shift register 44 to receive a new string of serial display data. As grid driver 40 scans, i.e., activates, pairs of grids 14, the display data is essentially simultaneously latched onto output lines 47, amplified by a series of amplifiers 49 and electrically coupled to corresponding anodes, causing those anodes in the activated grids to fluoresce. However, for the display data signals to be output to anodes 11 in this fashion, the anode drivers must be enabled. By applying a logic "low" data signal to the anode driver output enable (OE) input port 46, anode driver 16 will be enabled and the display data signals on output lines 47 will be electrically coupled through "AND" gates 48 to output lines 36. Note that input port 46 is inverted so that when processor 20 supplies a logic "low" data signal to that port, a logic "high" voltage is applied to "AND" gates 48. Typically, while the system is activated, anode drivers 16, 18 are continuously enabled either by a control signal or by a constant voltage (low) supplied to OE port 46.
Because grid driver 40 activates only two grids 14 at any instant in time (described in further detail below), anode drivers 16, 18 need only supply display data to the four columns of associated anodes at that time. Therefore, in a quad-anode connection structure, only four output lines 36, 37 need be provided per row of anodes 11 for an anode driver to supply display data to an entire row of anodes, so long as the display data on lines 36, 37 is changed in synchronism with the activation of each pair of grids. Thus, each four output lines 36, 37 associated with a row of anodes from one of anode drivers 16, 18 is connected to every fourth anode 11 in that associated row. For example, in the system of FIG. 1, output lines (a1, b1, c1, d1) 36 of left anode driver 16 are connected to the first four anodes 11 of the top row of anodes associated with the first two grids (G1 and G2) 14, each grid associated with two columns of anodes as described above. These same output lines (a1, b1, c1, d1) are connected in a similar fashion to the next four anodes in the top row of anodes, across grids G3 and G4, as well as across grids G5 and G6, and G7 and G8. This quad-anode connection is repeated for the connections between output lines 36 of left anode driver 16 and the top four rows of anodes. As a result, for simplified display 10 shown in FIG. 1, left anode driver 16 contains sixteen output lines 36 for selectively activating the top four rows of anodes 11. Similarly, right anode driver 18 has sixteen output lines 37 that are connected to the bottom four rows of anodes for selectively activating the bottom four rows of anodes.
With further reference to FIGS. 1, 2 and 3, operation of system 10 is described below. To display desired display data, processor 20 instructs grid driver 40 to scan grids G1-G8 14 while nearly simultaneously instructing anode drivers 16, 18 to transmit the display data, previously supplied by processor 20, to anodes 11 in matrix 12. Processor 20 initially loads grid data signals DG to a grid shift register (not shown) in grid driver 40 one bit at a time according to a grid clock signal CLKG applied to terminal 34. As discussed in further detail below, this grid data DG is strobed and latched to the output lines 42 of grid driver 40 to selectively scan grids 14. Then, processor 20 loads anode data D1 via port 22 (left anode driver 16) and D2 via port 24 (right anode driver 18) into corresponding anode shift registers 44 one bit at a time according to a clock signal CLK1 transmitted by processor 20 to each anode driver 16, 18.
With particular reference to the timing diagram shown in FIG. 2, after the grid and anode driver data has been loaded, but before the data has been strobed and latched to the respective output lines of drivers 16, 18, 40, processor 20 transmits a logic "high" grid blanking signal BLKG to grid driver 40 to disable all grids 14 corresponding to anodes 11 in matrix 12. With all grids 14 disabled, processor 20 applies an anode strobe signal STBA to a series of latch gates 45 in anode drivers 16, 18 via anode driver input ports 26, to latch anode data D1 and D2 from anode driver shift registers (44 for left anode driver 16, FIG. 3) to output lines 36, 37 of anode drivers 16, 18. Next, with all grids 14 still disabled, processor 20 transmits a grid strobe (latch) signal STBG to grid driver 40, thus latching grid data signals DG from grid shift register to a series of output lines of the latch gates (not shown) of grid driver 40 and allowing processor 20 to transmit the next string of grid data DG to the grid shift register. Finally, processor 20 pulls grid blanking signal BLKG to a logic "low" voltage level to place grid data DG on output lines 42 of grid driver 40, thus enabling the columns of anodes 11 associated with grids 14 activated by the grid data DG. When in this state, anodes associated with the activated grids will respond to data D1, D2 on output lines 36, 37 of anode drivers 16, 18, so long as the OE input port 46 of anode drivers 16, 18, connected to output lines 36, 37, is enabled.
One problem often associated with fluorescent display systems having closely spaced anodes is that the thermions emitted by the filament cathode sometimes "bleed" toward anodes that are associated with adjacent non-activated grids and that receive a logic "high" data signal, thus causing a "fuzzy" display. Even though the anodes 11 associated with inactive grids 14 are not enabled, those anodes are still susceptible to bleeding if they receive a logic "high" data signal from their respective anode drivers. To minimize this problem and provide a better defined, high quality display, some known systems, including system 10 shown in FIG. 1, use a quad-anode connection structure between anode drivers 16, 18 and anodes 11, in conjunction with a particular method of delivering the serial display data, including activating two grids 14 at a time, wherein selected columns of anodes 11 associated with the currently activated grids 14 are driven to a logic "low" voltage level while the remaining columns of anodes associated with the currently activated grids respond to the desired display data. To intentionally drive certain anodes "low" while allowing other anodes to respond to display data, such quad-anode display systems must modify the display data D1, D2 sent to anode drivers 16, 18.
More specifically, system 10 activates two grids 14 at a time by transmitting appropriate grid data signals DG to grid driver 40. Typically, grid data signals DG instruct grid driver 40 to successively activate adjacent pairs of grids, e.g., G1 and G2, G2 and G3, etc. As a result, system 10 may display four columns of data each time processor 20 transmits a logic "low" grid blanking signal BLKG, thus enabling grids G1-G8. For example, as grid driver activates grids G1 and G2 (FIG. 1), the four columns of anodes associated with those two activated grids 14 will respond to the display data D1, D2 that has been "latched" by processor 20 onto output lines 36, 37 of anode drivers 16, 18. Thereafter, based on control signal BLKG from processor 20, grid driver 40 successively activates adjacent pairs of grids G2 and G3, G3 and G4, etc., to G1 and G8 (this latter pair of grids being considered "adjacent" according to this description of the operation of this quad-anode system), each time enabling anodes 11 associated with the currently activated grids to respond to the display data D1, D2 on output lines 36, 37 of anode drivers 16, 18. In other words, every time grid driver 40 activates two successive grids 14, grid driver 40 enables four columns of anodes spanning two adjacent grids 14 of display matrix 12 to respond to four columns of display data D1, D2 to display the desired information.
In addition to enabling two grids 14 at a time, to minimize "bleeding" of thermions, known systems must modify the display data D1, D2 that processor 20 sends to anode drivers 16, 18. To understand why known systems must modify the display data, an illustrative example follows. With reference to FIG. 1, system 10 is displaying three numbers "5-3-4," in succession, spanning over five grids G1-G5 14 of display matrix 12.
When grid driver 40 activates grids G3 and G4, the anode associated with activated grid G4 that is connected to output line d2 of anode driver 16 (hereinafter "anode A.sub.2,8," "2" referring to the row and "8" referring to the column, C8) is supplied with a logic "high" data signal based on the data transmitted by processor 20 to anode driver 16, thus causing that anode to be activated and fluoresce, as it should. However, other anodes connected to output line d2 of anode driver 16, including the anode in row two of column C4 associated with grid G2 (hereinafter "anode A.sub.2,4 "), should not fluoresce. This becomes a problem because output line d2 of anode driver 16 is at logic "high" when grid driver 40 activates grids G3 and G4. As a result, even though anode A.sub.2,4 is associated with a non-active grid (grid G2), anode A.sub.2,4 may nevertheless attract thermions and fluoresce because, at that time, it is receiving a logic "high" data signal when grids G3 and G4 are active.
In other words, anodes 11 that should not be fluorescing at a particular instant may still attract thermions if they receive a logic "high" data signal from anode drivers 16, 18, even though those anodes themselves are associated with grids that are not activated. Note that anodes that should not be fluorescing will not likely fluoresce even when they are receiving a logic "high" data signal if they are in a non-activated grid that is not adjacent to an activated grid because they are far enough away from an activated grid that the chance that they will attract thermions is low. As suggested above, this bleeding of thermions typically will occur when the anode receiving a logic "high" data signal is associated with a non-activated grid 14 that is adjacent to an activated grid 14.
To minimize the above-defined bleeding problem associated with displaying four columns of data at once, known systems modify the display data. Specifically, known systems insure that the outer columns of anodes 11 associated with each pair of activated grids 14 (four columns of anodes) are all at logic "low" voltage levels. As a result, anodes associated with non-activated grids 14 adjacent to activated grids, that should not be fluorescing, will also be supplied a logic "low" signal and, therefore, will not likely fluoresce. Turning again to the "5-3-4" example of FIG. 1, system 10 modifies the display data so that output lines a2 and d2 receive a logic "low" data signal when grid driver 40 activates grids G3 and G4, thus minimizing the chance that anodes A.sub.2,4 and A.sub.2,9 will fluoresce. As grid driver 40 scans grids 14, system 10 modifies display data D1, D2 so that the inner two columns of anodes associated with each pair of activated grids 14 receive unmodified display data (i.e., data as input to system 10) while the outer two columns of lit anodes associated with those same two activated grids receive logic "low" data signals at any particular instant. In other words, when grid driver 40 activates grids G1 and G2, anodes in columns C2 and C3 respond to the unmodified portion of data D1, D2, while anodes in columns C1 and C4 receive and respond to the modified portion of display data which consists of logic "low" modified data signals. On the next scan, when grid driver 40 activates grids G2 and G3, inner columns C4 and C5 respond to the display data as input to system 10, while anodes in outer columns C3 and C7 receive and respond to the modified a data signals, which again are at logic "low."
Stated another way, by focusing on four output lines a1-d1, processor 20 modifies the display data D1, D2 and transmits that modified data to anode drivers 16, 18 so output lines a1 and d1 of anode driver 16 are at logic "low" while output lines b1 and c1 electrically couple the display data, as it was inputted to system 10, to corresponding anodes 11 when grid driver 40 activates grids G1 and G2. Thereafter, when grid driver 40 activates grids G2 and G3, system 10 modifies the data so lines b1 and c1 receive logic "low" data signals, while lines a1 and d1 receive and transmit the desired display data as it was inputted to system 10, in other words, lines a1 and d1 transmit the unmodified portion of the display data. As a result, as grid driver 40 scans grids 14, thermions do not "bleed" toward anodes associated with non-enabled grids that are adjacent to enabled grids because those anodes will not receive logic "high" data signals even though they would be receiving a logic "high" data signal but for the modification of the display data. Therefore, a clear display results.
Although, the above-described method minimizes thermion bleeding, it comes at the expense of processor time. Known quad-anode systems, such as that described above, modify the display data in the following manner. Upon receipt of serial display data, processor 20 places data D1, D2 in a first memory location and, thereafter, transmits the data to a temporary memory location, i.e., a buffer, so that the first memory location may receive a new string of serial data. Then, processor 20 modifies the data in the temporary memory location by performing an "AND" mask operation on the data to "zero out" particular bits of data in the serial string, consistent with the above description. Specifically, because processor 20 synchronizes transmittal of display data and grid data, processor 20 is able to "mask," i.e., "zero out," the bits of data corresponding to anodes in the outer columns of anodes in grids 14 that are activated at that particular time.
For example, when a string of serial data is sent to processor 20 in the form "11111111 . . . ," processor 20 performs the "AND" mask operation, and then transmits the data to anode drivers 16, 18. (Note that the series of "1"'s represents a string of data bits (all turned on); of course, the bits could be high, logic "1," or low, logic "0.") As a result of this operation, the first string of data sent to the anode driver will read "01100110 . . . ," wherein each "0" represents a data bit that has been "masked" by the "AND" operation and each "1" represents a bit of data that is not masked by the system. Therefore, when grid driver 40 activates G1 and G2 on the first deactivation of grid blanking signal BLKG, the data in columns one and four will be masked (output lines a1 and d1 of anode driver 16 will be at logic "low"), thus anodes 11 in those columns cannot receive a logic "high" data signal and will not fluoresce, even though the unmodified display data would dictate that those anodes should be active.
On the next grid blanking signal, BLKG "low", thus activating G2 and G3, processor 20 will have sent serial display data to anode drivers 16, 18 that reads "10011001 . . . ," processor 20 will have masked the display data for columns C3 and C6 (in the then activated grids G2 and G3) with the "AND" operation, while leaving the data for columns C4 and C5 unmasked (FIG. 1). As a result, the bleeding problem is minimized because each anode associated with a grid that is adjacent to the currently active grids, and which is connected to a data line 36, 37 that is in common with an anode associated with an active grid that is receiving a masked bit of data, cannot receive a logic "high" data signal and, therefore, not fluoresce. Therefore, anodes such as anode A.sub.2,4 in the above-described example will not be active and will not attract thermions.
For a typical display that has sixteen rows of anodes and two anode drivers that each supply data for one-half of the rows of the display, each anode driver has thirty-two output lines, four for each row of anodes. As a result, thirty-two bits of masked data are sent from processor 20 to anode drivers 16, 18 each time grid driver 40 activates a successive pair of grids 14.
In sum, to display four columns of data in known quad-anode driving systems (in the example immediately above, data for columns two, three, four, and five), processor 20 must send the display data two times, a first time when grid driver 40 activates G1 and G2 (columns C2 and C3) and a second time when grid driver 40 activates G2 and G3 (columns C4 and C5). Also, to minimize "bleeding" of thermions and the attendant fuzzy display, each time processor 20 transmits display data, processor 20 must mask the data to be displayed on the outer columns of anodes associated with each pair of activated grids 14 while anodes associated with the inner columns of anodes respond to the desired unmasked display data.
Therefore, known quad-anode display driving systems have two primary drawbacks that make them inefficient and in some cases expensive to manufacture. First, the processor must perform an "AND" mask operation, thus utilizing valuable processor time. Second, for four columns of anodes to respond to unmasked data, processor 20 must transmit data to both anode drivers two times, similarly utilizing valuable processor time. To perform these functions in certain applications, as in an automobile environment, a separate dedicated processor typically is desired, as opposed to the on-board processor of the vehicle, thus further adding to the inefficiency and expense of known systems.
Therefore, the vacuum fluorescent display market is in need of a quad-anode driver that utilizes a minimum number of required components and which is capable of transmitting and displaying four columns of (unmasked) data with a minimum amount of processing time. With a given CPU speed, the importance of these features increases with the size of the VFD matrix. Preferably, the system will operate in conjunction with the on-board processor of, for example, a vehicle (i.e., without an independent dedicated processor), to drive the anode pixel information of the VFD as fast as possible, while leaving valuable processor time to simultaneously and efficiently perform a variety of other necessary tasks.